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Ordering number : EN*5785
CMOS LSI
LC895297
Full CAV 20x CD-ROM Decoder with Built-in ATA-PI (IDE) Interface and CD-DSP
Preliminary Overview
The LC895297 is a single-chip CD-ROM decoder and CD-DSP system that supports full CAV 20x operation and includes a built-in ATA-PI (IDE) interface. I/O channel. * Performs unscrambling and de-interleaving to reorder the demodulated EFM signal in the prescribed manner. * Performs error code detection and correction, and flag processing. (C1: dual errors, C2: four errors) * Sets the C2 flags based on the C1 flags and a C2 check, and performs interpolation or muting depending on the C2 flags. Adopts a 2-point interpolation circuit, and converges the signal to the muting level if the C2 flags indicate over 2 consecutive uncorrectable errors. * Accepts the input of commands from a control microprocessor over an 8-bit parallel interface. Supports track jump, disc motor start/stop, muting on/off, and track counting commands. * Can perform arbitrary track counts. * Includes CAV audio functions. * Adopts zero-cross muting. * Includes 8x oversampling digital filters. * D/A converter with PWM output. * Includes independent left and right channel digital attenuators. * Provides digital deemphasis. * Supports bilingual functions.
Functions
* Full CAV 20x CD-DSP and CD-ROM decoder functions with built-in ATA-PI (IDE) interface
Features
[CD-ROM Decoder and ATA-PI (IDE) Interface Blocks] * * * * * * Full CAV 20x operation ATA-PI (IDE) interface Supports the use of EDO DRAM. Supports the use of up to 4 Mbits of buffer RAM. The user can set up arbitrary CD main channel and C2 flag areas in buffer RAM. Batch transfer function (function that automatically transfers the CD main channel and C2 flag data in a single operation.) Multi-block transfer function (function that automatically transfers multiple blocks in a single operation.) DVD ECC interface Intelligent functions
*
* *
Package Dimensions
unit: mm 3230-SQFP176
[LC897297]
[CD-DSP Block] * The IC inputs a high-frequency signal, slices that signal at the correct level, converts that result to an EFM coded signal, and compares the phase with that of the built-in VCO. * Uses an external 16.9344-MHz crystal element to generate a standard clock and to correctly generate the required internal timings. * Performs frame synchronization, signal detection, protection, and insertion, and assures stable data readout. * Demodulates the EFM coded signal to produce 8-bit symbol data. * After applying a CRC check to the subcode Q signal, outputs that signal to a microprocessor over a parallel
SANYO: SQFP176
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
22898HA (OT) No. 5785-1/9
LC895297
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input and output voltage Allowable power dissipation Operating temperature Storage temperature Soldering conditions (pins only) Input and output current II, IO Symbol VDD max VI, VO Pd max Topr Tstg 10s Per individual input or output cell Ta 70C *1 Conditions Ratings -0.3 to +7.0 -0.3 to VDD+0.3 500 -30 to +70 -55 to +125 235 20 Unit V V mW C C C mA
Note 1: Applications that use this IC must adopt heat dissipation measures, such as the insertion of a thermally conductive sheet.
Allowable Operating Ranges at Ta = -30 to +70C, VSS = 0 V
Parameter [Input and Output Cell Power Supply] Supply voltage Input voltage range [Internal Cell Power Supply] Supply voltage Input voltage range VDD VIN 3.9 0 4.0 4.1 VDD V V VDD VIN 4.5 0 5.0 5.5 VDD V V Symbol Conditions Ratings min typ max Unit
Electrical Characteristics at Ta = -30 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V
Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output low-level voltage Output low-level voltage Input leakage current Output leakage current Pull-up resistance Symbol VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL VOL VOL IIL IOZ RUP CMOS levels: Applicable pins: (4) Schmitt inputs. IOH = -2 mA: Applicable pins: (5), (1), (9), (10), and (15) IOL = 2 mA: Applicable pins: (5), (1), (9), (10), and (15) IOH = -4 mA: Applicable pins: (3) and (6) IOL = 24 mA: Applicable pins: (3) and (6) IOL = 2 mA: Applicable pins: (7) and (11) IOL = 24 mA: Applicable pins: (12) VI = VSS, VDD: Applicable pins: (2), (3), (4), (10), and (15) In high-impedance output mode: Applicable pins: (3), (6), (7), (9), (10), (12), and (15) Applicable pins: (1) and (11) -10 -10 40 80 VDD - 2.1 0.4 0.4 0.4 +10 +10 160 VDD - 2.1 0.4 0.8 VDD 0.2 VDD Conditions Ratings min 2.2 TTL levels. Applicable pins: (10) and (13) TTL levels. Applicable pins: (1) Pull-up resistor included. TTL levels. Applicable pins: (2), (3), and (15) Schmitt inputs. CMOS levels: Applicable pins: (14) 0.7 VDD 0.3 VDD 2.4 0.8 2.2 0.8 V V V V V V V V V V V V A A k 0.8 typ max Unit V V V
The applicable pin sets are as follows: [INPUT] (2) ZRESET, ZDMACK, ZHRST, DA0to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, FG (4) ZCSCTRL, ZCS, ZRD, ZWR, HFL, TES (14) DEFI (13) SUA0 o SUA6 [OUTPUT] (6) DMARQ, HINTRQ (5) RA0 to RA8, ZRAS0, ZCAS0, ZOE, ZUWE, ZLWE, C2F, ROMXA, FSX, EFLG, PCK, FSEQ, TOFF, TGL, 4.2M, WRQ, RWC, COIN, ZCQCK, RCHP, RCHN, LCHP, LCHN (7) ZRSTCPU, ZRSTIC (9) JP+, JP-, SPO (11) ZINT0, ZINT1, ZSWAIT Continued on next page. (12) IORDY, ZIOCS16
No. 5785-2/9
LC895297
Continued from preceding page.
[INOUT] (1) D0 to D7, IO0 to IO15 (3) DD0 to DD15, ZDASP, ZPDIAG (10) IOP0 to IOP7 (15) DRESP, DREQ Note: XTAL, XTALCK, R0, VCNT0, PDO0, R1, VCNT1, PO11, PO21, BSN1, R2, VCNT2, PO12, PO22, and BSN2 The above pins are not covered by the electrical characteristics. The 1-bit D/A converter block pins are only measured using a logic tester; no analog measurements are performed.
EFM Input and Output Signals Electrical Characteristics at Ta = -30 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V
Parameter Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Input leakage current Output leakage current Symbol VIH VIL VOH VOL IIL IOZ Conditions Ratings min 3.2 1.8 VDD - 2.1 0.4 -10 -10 +10 +10 typ max Unit V V V V A A
Micro-signal amplifier. Applicable pins: EFMI IOH = -4 mA. Applicable pins: EFMO and ZEFMO IOL = 4 mA. Applicable pins: EFMO and ZEFMO VI = VSS, VDD: Applicable pins: EFMI In high-impedance mode: Applicable pins: EFMO and ZEFMO
External Clock Generator PLL Circuit
Figure 1 PLL Circuit
Symbol R1 R2 R3 C1 C2
Currently used value 7.5 k 10 k 200 0.1 F 0.1 F
Notes VCO adjustment resistor Low-pass filter resistor Low-pass filter phase compensation resistor Low-pass filter capacitor VCO bias stabilization capacitor
While the circuit structure is fixed, the values of the components will vary with the circuit board capacitance and other application circuit parameters.
No. 5785-3/9
LC895297 Block Diagram
DVD interface
IDE interface
External buffer RAM
*1 *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12 *13 *14 **1
DEFI, EFMI, HFL, TES 4.2M, EFMO, PCK, FSEQ, TOFF, TGL, JP+, JP-, RWC, COIN, ZCQCK RCHP, RCHN, LCHP, LCHN DD0 to DD15, ZDASP, ZPDIAG ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK, ZHRST DMARQ, HINTRQ, ZIOCS16, IORDY ZRD, ZWR, ZCS, ZCSCTRL, SUA0 to SUA6 D0 to D7 IO0 to IO15 RA0 to RA8, ZRAS0, ZCAS0, ZOE, ZUWE, ZLWE DREQ DRESP IOP0 to IOP7 R0, VCNT0, PDO0 HISIDE (WD25C32) is made by WESTERN DIGITAL
No. 5785-4/9
LC895297 Pin Functions
I : Input pin, O: Output pin, B : Bidirectional pin, P: Power supply pin, NC: Not connected Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 ZRSTCPU ZRSTIC ZRESET D7 D6 D5 D4 D3 D2 D1 D0 Pin name AVSS0 R0 VCNT0 PDO0 TEST0 TEST1 IOP0 (HDB7) IOP1 (HDB6) IOP2 (HDB5) IOP3 (HDB4) IOP4 (HDB3) IOP5 (HDB2) IOP6 (HDB1) IOP7 (HDB0) VDD2 TEST3 TEST4 DRESP DREQ RCHP RCHN VDD1 VSS1 LCHP LCHN VSS0 XTALCK XTAL VSS0 Type P I I O I I B B B B B B B B P I I I O O O P P O O P I O P NC O O I B B B B B B B B Microcontroller data signal connection. These pins include built-in pull-up resistors. CPU reset signal output Drive IC reset signal output IC reset input Crystal oscillator circuit input (16.9344 MHz) Crystal oscillator circuit output 4.0 V Test pin Test pin DVD ECC data latch signal input DVD ECC data request output 1-bit D/A converter right channel P output 1-bit D/A converter right channel N output 1-bit D/A converter left and right channel power supply 1-bit D/A converter right channel ground 1-bit D/A converter left channel P output 1-bit D/A converter left channel N output General-purpose I/O ports These pins are used for DVD ECC data input when the DVD interface is used. VCO bias resistor connection VCO control voltage input Charge pump output Test pins Function
Continued on next page.
No. 5785-5/9
LC895297
Continued from preceding page.
I : Input pin, O: Output pin, B : Bidirectional pin, P: Power supply pin, NC: Not connected Pin No. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Pin name SUA0 SUA1 VDD0 VSS0 VDD2 SUA2 SUA3 SUA4 SUA5 SUA6 ZCSCTRL ZCS ZSWAIT ZWR ZRD ZINT0 ZINT1 WRQ FSEQ C2F ROMXA FSX (CK2) EFLG (LRSY) FG VDD2 VSS0 TEST2 ZEFMO EFMO EFMI VDD0 JP- JP+ TGL TOFF TES HFL NC SPO DEFI 4.2M R1 BSN1 VCNT1 PO11 PO21 AVDD1 AVSS1 O I O I I I O O P P 4.0 V CAV control output Defect detection signal input 4.2336-MHz output VCO bias resistor connection Charge pump bias resistor connection VCO control voltage Charge pump outputs Type I I P P P I I I I I I I O I I O O O O O O O O I P P I O O I P O O O O I I Tracking gain switching output Tracking off output Tracking error signal input. Schmitt input Tracking detection signal input. Schmitt input Test pin Inverted EFM signal output EFM signal output EFM signal input 5V Track jump output Microcontroller chip select active-low/high selection Register chip select signal input (from the microcontroller) Wait signal output (to the microcontroller) Data write signal input (from the microcontroller) Data read signal input (from the microcontroller) Interrupt request signal output (to the microcontroller) Subcode Q output standby output Synchronization signal detection output C2 flag output for ROMXA Interpolation data output for ROMXA 7.35-kHz signal output (Bit clock output for ROMXA) C1 and C2 error correction monitor output (LRSY output for ROMXA) FG pulse input for CAV control 4.0 V Microcontroller register selection 4.0 V 5V Microcontroller register selection Function
Continued on next page.
No. 5785-6/9
LC895297
Continued from preceding page.
I : Input pin, O: Output pin, B : Bidirectional pin, P: Power supply pin, NC: Not connected Pin No. 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 ZCQCK COIN RWC ZRAS0 ZCAS0 ZOE VSS0 ZUWE ZLWE RA0 RA1 RA2 VDD0 VSS0 RA3 RA4 RA5 RA6 RA7 RA8 IO8 IO9 IO10 VSS0 IO11 IO12 IO13 IO14 IO15 IO7 IO6 IO5 IO4 IO3 VDD2 VSS0 IO2 IO1 IO0 Pin name R2 BSN2 VCNT2 PO12 PO22 VDD2 PCK Type I I I O O P O NC O O O O O O P O O O O O P O O O O O O O B B B P B B B B B B B B B B P P B B B Data buffer RAM data input and output These pins include built-in pull-up resistors. 4.0 V Data buffer RAM data input and output These pins include built-in pull-up resistors. Data buffer RAM data input and output These pins include built-in pull-up resistors. Data buffer RAM address signal outputs 5V Data buffer RAM address signal outputs Buffer RAM upper write enable Buffer RAM lower write enable ASP command acquisition clock output ASP command output Output to the ASP read/write control input Buffer RAM RAS signal output Buffer RAM CAS signal output Buffer RAM output enable 4.0 V EFM data reproduction bit clock monitor VCO bias resistor connection Charge pump bias resistor connection VCO control voltage Charge pump outputs Function
Continued on next page.
No. 5785-7/9
LC895297
Continued from preceding page.
I : Input pin, O: Output pin, B : Bidirectional pin, P: Power supply pin, NC: Not connected Pin No. 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Pin name ZHRST VSS2 DD7 DD8 DD6 DD9 VDD0 VSS2 DD5 DD10 DD4 DD11 VSS2 DD3 DD12 DD2 DD13 VDD0 VSS2 DD1 DD14 DD0 DD15 VSS2 DMARQ ZDIOW ZDIOR IORDY ZDMACK HINTRQ ZIOCS16 VSS2 DA1 ZPDIAG DA0 DA2 ZCS1FX ZCS3FX ZDASP AVDD0 Type I P B B B B P P B B B B P B B B B P P B B B B P O I I O I O O P I B I I I I B P 4.0 V ATAPI control signal ATAPI control signal ATAPI data bus 5V ATAPI data bus ATAPI data bus 5V ATAPI data bus ATAPI control signal Function
Pin names that start with the letter Z are negative-logic signals. The following power-supply voltages must be provided; VDD0: 5 V, VDD1 (for the 1-bit D/A converter): 5 V, and VDD2: 4.0 V. VSS0 is the logic system ground, VSS1 is the 1-bit D/A converter ground, and VSS2 is the IDE interface drive ground.
No. 5785-8/9
LC895297 Thermal Design Since this IC supports operation at up to 20x speeds, it operates at extremely high speeds internally. Applications must take measures to dissipate the heat that results from this high-speed operation. IC operation is not guaranteed if adequate heat dissipation measures are not taken. Heat Dissipation Example
Steel plate
Thermally conductive sheet
Applications must be designed with a thermally conductive sheet above the LC895297 and the LC895297 positioned so that the system chassis contacts the thermally conductive sheet.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1998. Specifications and information herein are subject to change without notice. PS No. 5785-9/9

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